Graduate Course Proposal Form Submission Detail - EEL6728
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Approved by SCNS
Submission Type: Change
Course Change Information (for course changes only): Remove all undergraduate prerequisites.
Comments: Elective for Electrical Eng. To GC. Form incomplete. Back to edit queue. Emailed 3/11/16. Form complete 5/8/16. To GC (Removing Pre-req only). Approved 5/11/16 To USF Sys 5/18/16; to SCNS after 5/25/16. Apprd eff 7/1/16
- Department and Contact Information
Tracking Number Date & Time Submitted 5255 2015-09-02 Department College Budget Account Number Electrical Engineering EN 210600 Contact Person Phone Jessica Procko 8139746318 firstname.lastname@example.org
- Course Information
Prefix Number Full Title EEL 6728 Intro to VHDL Is the course title variable? N Is a permit required for registration? N Are the credit hours variable? N Is this course repeatable? If repeatable, how many times? 0 Credit Hours Section Type Grading Option 3 C - Class Lecture (Primarily) R - Regular Abbreviated Title (30 characters maximum) Intro to VHDL Course Online? Percentage Online C - Face-to-face (0% online) 0
An in-depth study of the VHDL hardware description language with emphasis on digital circuit simulation and digital design for synthesis.
A. Please briefly explain why it is necessary and/or desirable to add this course.
B. What is the need or demand for this course? (Indicate if this course is part of a required sequence in the major.) What other programs would this course service?
Part of multiple tracks within the EE department
C. Has this course been offered as Selected Topics/Experimental Topics course? If yes, how many times?
Yes, 3 or more times
D. What qualifications for training and/or experience are necessary to teach this course? (List minimum qualifications for the instructor.)
- Other Course Information
Making an in-depth analysis of the syntax of VHDL.
Acquiring skills in Digital Design using hardware description languages.
Analyzing synthesizable RTL VHDL code for digital design using dataflow, structural, and behavioral coding styles.
Describing and applying good programming style in VHDL
Obtaining knowledge and skills in the use of digital circuit simulation software tools
Developing and implementing a methodology for the creation of test bench programs in VHDL.
Implement a methodology for the creation of FSMs in VHDL.
B. Learning Outcomes
After successful completion of this course students will be able to:
Design, model and analyze basic digital circuits using VHDL.
Design, implement and test FSMs using VHDL
Conduct simulations and testing of complex digital designs using VHDL tools.
Identify and describe the different phases of the design flow for digital hardware using VHDL.
Point out the synthesizable subset of VHDL.
Determine if a VHDL code is intended for simulation or synthesis.
Compare and identify similarities and differences between the two main Hardware Description Languages: VHDL and SystemVerilog.
C. Major Topics
Digital Design review
Introduction to VHDL
Simulation with VHDL Testbenches
VHDL Design of State Machines
Comparison of VHDL and SystemVerilog
Good VHDL coding practices
VHDL Design with Basic Displays
Pedroni V. Circuit Design and Simulation with VHDL. MIT Press, 2010.
E. Course Readings, Online Resources, and Other Purchases
Additional course readings will be identified and posted on Canvas
F. Student Expectations/Requirements and Grading Policy
Quizzes and Homework: 10 %; 2 Tests: 50 %, 3 Projects: 40 %
G. Assignments, Exams and Tests
Quizzes and Homework 10%
Projects 40 %
Midterm exam 25 %
Final exam 25 %
H. Attendance Policy
Course Attendance at First Class Meeting Policy for Graduate Students: For structured courses, 6000 and above, the College/Campus Dean will set the first-day class attendance requirement. Check with the College for specific information. This policy is not applicable to courses in the following categories: Educational Outreach, Open University (TV), FEEDS Program, Community Experiential Learning (CEL), Cooperative Education Training, and courses that do not have regularly scheduled meeting days/times (such as, directed reading/research or study, individual research, thesis, dissertation, internship, practica, etc.). Students are responsible for dropping undesired courses in these categories by the 5th day of classes to avoid fee liability and academic penalty. (See USF Regulation Registration - 4.0101,
In the event of an emergency, it may be necessary for USF to suspend normal operations. During this time, USF may opt to continue delivery of instruction through methods that include but are not limited to: Blackboard, Elluminate, Skype, and email messaging and/or an alternate schedule. Its the responsibility of the student to monitor Blackboard site for each class for course specific communication, and the main USF, College, and department websites, emails, and MoBull messages for important general information.
I. Policy on Make-up Work
Late Project Submission without documented circumstance beyond students control will be accepted one week past due date and will receive a 20 % grade deduction.
J. Program This Course Supports
Electrical Engineering MSEE/PhD
- Course Concurrence Information