Graduate Course Proposal Form Submission Detail - EEL6729
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Approved by SCNS
Submission Type: New
Course Change Information (for course changes only):
Comments: For Electrical Eng - Elective. Repeatable up to 3 times. GC appd 2/11/15. To USF Sys 2/27/15. Nmbr 6390 approved as 6729. Effective 4/1/15
- Department and Contact Information
Tracking Number Date & Time Submitted 5135 2014-11-03 Department College Budget Account Number Electrical Engineering EN 2106000 Contact Person Phone Jessica Procko 8139746318 email@example.com
- Course Information
Prefix Number Full Title EEL 6729 Rapid System Prototyping Is the course title variable? N Is a permit required for registration? N Are the credit hours variable? N Is this course repeatable? If repeatable, how many times? 0 Credit Hours Section Type Grading Option 3 C - Class Lecture (Primarily) R - Regular Abbreviated Title (30 characters maximum) Rapid System Prototyping Course Online? Percentage Online C - Face-to-face (0% online) 0
Focus on digital synthesis targeting FPGAs as a way of obtaining rapid prototypes of digital circuits.
A. Please briefly explain why it is necessary and/or desirable to add this course.
Replacing Selected Topics with Permanent number; already listed in program
B. What is the need or demand for this course? (Indicate if this course is part of a required sequence in the major.) What other programs would this course service?
Part of multiple tracks of study within the EE department
C. Has this course been offered as Selected Topics/Experimental Topics course? If yes, how many times?
Yes, 3 or more times
D. What qualifications for training and/or experience are necessary to teach this course? (List minimum qualifications for the instructor.)
Ph.D. in Electrical Engineering with emphasis on CMOS/VLSI Digital Design.
- Other Course Information
To move from knowledge of VHDL in the simulation domain to practical synthesis, implementation and testing of VHDL based designs in hardware.
To implement Rapid Prototyping utilizing VHDL logic synthesis and in-circuit programmable FPGAs which allows the creation of complex system architectures that previously required an extended design cycle.
To familiarize the students with a broad range of topics critical to rapid system prototyping including system design, design approach, clear coding techniques, model architecture selection, code reuse, code documentation, synthesis and debug, simulation, debug and downloading the design to a prototype board for debug and functional verification.
To develop and synthesize practical applications in FPGAs.
B. Learning Outcomes
After successful completin of this curse students will be able to:
Explain the architecture of a typical (XILINX) PFGA.
Describe the different steps in a digital synthesis process.
Transform the VHDL code of a digital design into a schematic diagram showing entities, ports, signals and their hierarchical relationships.
Extract a graphical representation of FSM's from the VHDL code of a digital design and identify states, operations in the states, and transition conditions.
Show expertise in the design, synthesis, and implementation of digital circuits using FPGAs as targets.
Summarize the relationships between digital simulation and digital synthesis.
C. Major Topics
FPGA architecture overview.
Phases of Rapid System Prototyping.
VHDL synthesis and hardware implementation.
Industry trends in FPGAs and Rapid Prototyping.
System-oriented design approach.
Digital Design with basic Displays.
Using the internal RAM and ROM memories in the FPGA
FPGA interface to flash memories
FPGA interface with USB
FPGA interface with HDMI
Hands-on experience on practical projects.
Proposed (but not limited to) Applications:
Digital Signal processing,
Software defined radio,
Digital control, etc.
Lee S. Advanced Digital Logic Design: using VHDL, State Machines, and Synthesis for FPGAs. Thompson, 2006.
E. Course Readings, Online Resources, and Other Purchases
Additional course readings will be identified and posted on Canvas
F. Student Expectations/Requirements and Grading Policy
Labs and Quizzes and Homework, 50 %; Test, 20 %, 3 Projects, 30 %
G. Assignments, Exams and Tests
Students attending this course will take 1 written test (20%).
Course Participants will implement, synthesize and analyze a series of Laboratory practices involving practical design applications using an FPGA board. (50%)
Students attending this course are required to implement and submit 2 projects involving design and simulation and synthesis of digital circuits using VHDL and targeting FPGAs (30%).
H. Attendance Policy
Course Attendance at First Class Meeting Policy for Graduate Students: For structured courses, 6000 and above, the College/Campus Dean will set the first-day class attendance requirement. Check with the College for specific information. This policy is not applicable to courses in the following categories: Educational Outreach, Open University (TV), FEEDS Program, Community Experiential Learning (CEL), Cooperative Education Training, and courses that do not have regularly scheduled meeting days/times (such as, directed reading/research or study, individual research, thesis, dissertation, internship, practica, etc.). Students are responsible for dropping undesired courses in these categories by the 5th day of classes to avoid fee liability and academic penalty. (See USF Regulation Registration - 4.0101,
Attendance Policy for the Observance of Religious Days by Students: In accordance with Sections 1006.53 and 1001.74(10)(g) Florida Statutes and Board of Governors Regulation 6C-6.0115, the University of South Florida (University/USF) has established the following policy regarding religious observances: (http://usfweb2.usf.edu/usfgc/gc_pp/acadaf/gc10-045.htm)
In the event of an emergency, it may be necessary for USF to suspend normal operations. During this time, USF may opt to continue delivery of instruction through methods that include but are not limited to: Blackboard, Elluminate, Skype, and email messaging and/or an alternate schedule. Its the responsibility of the student to monitor Blackboard site for each class for course specific communication, and the main USF, College, and department websites, emails, and MoBull messages for important general information.
I. Policy on Make-up Work
Late project submission: Late Lab or Project Submission without documented circumstance beyond students control will be accepted one week past due date and will receive a 20 % grade deduction.
J. Program This Course Supports
Electrical Engineering MSEE/PhD
- Course Concurrence Information