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Graduate Course Proposal Form Submission Detail - EEL6728

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Current Status: Approved by SCNS - 2015-04-01
Campus: Tampa
Submission Type: New
Course Change Information (for course changes only):
Comments: For Electrical Eng - Elective. GC appd 2/10/15. To USF Sys 2/27/15. Nmbr 6725 approved as 6728. Effective 4/1/15


  1. Department and Contact Information

    Tracking Number Date & Time Submitted
    5134 2014-11-03
     
    Department College Budget Account Number
    Electrical Engineering EN 2106000
     
    Contact Person Phone Email
    Jessica Procko 8139746318 jprocko@usf.edu

  2. Course Information

    Prefix Number Full Title
    EEL 6728 Intro to VHDL

    Is the course title variable? N
    Is a permit required for registration? N
    Are the credit hours variable? N
    Is this course repeatable?
    If repeatable, how many times? 0

    Credit Hours Section Type Grading Option
    3 C - Class Lecture (Primarily) R - Regular
     
    Abbreviated Title (30 characters maximum)
    Intro to VHDL
     
    Course Online? Percentage Online
    C - Face-to-face (0% online) 0

    Prerequisites

    EEL 4705; EEL 4705L

    Corequisites

    Course Description

    An in-depth study of the VHDL hardware description language with emphasis on digital circuit simulation and digital design for synthesis.


  3. Justification

    A. Please briefly explain why it is necessary and/or desirable to add this course.

    Replacing Selected Topics with Permanent number; already listed in program

    B. What is the need or demand for this course? (Indicate if this course is part of a required sequence in the major.) What other programs would this course service?

    Part of multiple tracks within the EE department

    C. Has this course been offered as Selected Topics/Experimental Topics course? If yes, how many times?

    Yes, 3 or more times

    D. What qualifications for training and/or experience are necessary to teach this course? (List minimum qualifications for the instructor.)


  4. Other Course Information

    A. Objectives

    • Making an in-depth analysis of the syntax of VHDL.

    • Acquiring skills in Digital Design using hardware description languages.

    • Analyzing synthesizable RTL VHDL code for digital design using dataflow, structural, and behavioral coding styles.

    • Describing and applying good programming style in VHDL

    • Obtaining knowledge and skills in the use of digital circuit simulation software tools

    • Developing and implementing a methodology for the creation of test bench programs in VHDL.

    • Implement a methodology for the creation of FSM’s in VHDL.

    B. Learning Outcomes

    After successful completion of this course students will be able to:

    • Design, model and analyze basic digital circuits using VHDL.

    • Design, implement and test FSMs using VHDL

    • Conduct simulations and testing of complex digital designs using VHDL tools.

    • Identify and describe the different phases of the design flow for digital hardware using VHDL.

    • Point out the synthesizable subset of VHDL.

    • Determine if a VHDL code is intended for simulation or synthesis.

    • Compare and identify similarities and differences between the two main Hardware Description Languages: VHDL and SystemVerilog.

    C. Major Topics

    • Digital Design review

    • Introduction to VHDL

    • Code Structure

    • Data Types

    • Operators

    • Attributes

    • Concurrent Code

    • Sequential Code

    • Signal

    • Variable

    • Package

    • Component

    • Function

    • Procedure

    • Simulation with VHDL Testbenches

    • VHDL Design of State Machines

    • Comparison of VHDL and SystemVerilog

    • Good VHDL coding practices

    • VHDL Design with Basic Displays

    D. Textbooks

    Pedroni V. Circuit Design and Simulation with VHDL. MIT Press, 2010.

    E. Course Readings, Online Resources, and Other Purchases

    Additional course readings will be identified and posted on Canvas

    F. Student Expectations/Requirements and Grading Policy

    Quizzes and Homework: 10 %; 2 Tests: 50 %, 3 Projects: 40 %

    G. Assignments, Exams and Tests

    Quizzes and Homework 10%

    Projects 40 %

    Midterm exam 25 %

    Final exam 25 %

    H. Attendance Policy

    Course Attendance at First Class Meeting – Policy for Graduate Students: For structured courses, 6000 and above, the College/Campus Dean will set the first-day class attendance requirement. Check with the College for specific information. This policy is not applicable to courses in the following categories: Educational Outreach, Open University (TV), FEEDS Program, Community Experiential Learning (CEL), Cooperative Education Training, and courses that do not have regularly scheduled meeting days/times (such as, directed reading/research or study, individual research, thesis, dissertation, internship, practica, etc.). Students are responsible for dropping undesired courses in these categories by the 5th day of classes to avoid fee liability and academic penalty. (See USF Regulation – Registration - 4.0101,

    http://usfweb2.usf.edu/usfgc/ogc%20web/currentreg.htm)

    Attendance Policy for the Observance of Religious Days by Students: In accordance with Sections 1006.53 and 1001.74(10)(g) Florida Statutes and Board of Governors Regulation 6C-6.0115, the University of South Florida (University/USF) has established the following policy regarding religious observances: (http://usfweb2.usf.edu/usfgc/gc_pp/acadaf/gc10-045.htm)

    In the event of an emergency, it may be necessary for USF to suspend normal operations. During this time, USF may opt to continue delivery of instruction through methods that include but are not limited to: Blackboard, Elluminate, Skype, and email messaging and/or an alternate schedule. It’s the responsibility of the student to monitor Blackboard site for each class for course specific communication, and the main USF, College, and department websites, emails, and MoBull messages for important general information.

    I. Policy on Make-up Work

    Late Project Submission without documented circumstance beyond students control will be accepted one week past due date and will receive a 20 % grade deduction.

    J. Program This Course Supports

    Electrical Engineering MSEE/PhD


  5. Course Concurrence Information



- if you have questions about any of these fields, please contact chinescobb@grad.usf.edu or joe@grad.usf.edu.